The use of metal silicide layers in CMOS devices offers several advantages in device performance. For example, in a gate structure 10 as shown in FIG. 1, a portion of the gate material 15 immediately above the gate dielectric 13 may be replaced by a silicide material. More recently, advanced devices have been produced with fully silicided gates; that is, the entire gate structure above the gate dielectric is replaced by a silicide material. In a typical gate structure made of polysilicon, this involves covering the polysilicon with a blanket layer of metal and performing a silicidation process (details of which are known to those skilled in the art). To achieve full silicidation of all the gate structures on a wafer, a high degree of uniformity is required in the height of the gate structures. The gate structure height is typically controlled by planarization (chemical mechanical polishing or CMP) and/or an etchback process. However, CMP and etchback processes present manufacturing difficulties, particularly when the CMOS devices are being produced on large wafers (e.g. 300 mm diameter). These processes cannot provide the required cross-wafer polysilicon height uniformity; this leads to low quality of the silicided gates and low device yields. In addition, the conventional fully-silicided gate formation process requires many more process steps in comparison to the process for making standard polysilicon CMOS gates.
Accordingly, there is a need for a process which provides fully silicided CMOS gate structures while avoiding the uniformity problem associated with current techniques. In addition, it is desirable that the process have fewer steps than are used at present.